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12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 19-5756; rev 2; 5/13 simplified block diagram general description the MAX9679 provides multiple programmable reference voltages for gamma correction in tft lcds and a programmable reference voltage for vcom adjustment. all gamma and vcom reference voltages have a 10-bit digital-to-analog converter (dac) and high- current buffer, which reduces the recovery time of the output voltages when critical levels and patterns are displayed. a programmable internal reference sets the full-scale voltage of the dacs. two independent sets of gamma curves and vcom codes can be stored in the ic's volatile memory; bksel signal selects between the two sets. the ic has multiple-time programmable (mtp) memory to store gamma and vcom codes on the chip, eliminat - ing the need for external eeprom. applications tft lcds features s 12 channels of programmable gamma voltages with 10-bit resolution s programmable vcom voltage with 10-bit resolution s programmable reference for dacs s multiple-time programmable memory to store gamma and vcom codes s switching between two gamma curves and vcom voltages s avdd1, avdd2, and avdd_amp supplies to reduce heat s i 2 c interface (1mhz fast-mode plus) + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. ordering information i 2 c bksel gamma outputs vcom output MAX9679 prog re f prog re f vcom1 vcom2 gamma bank 1 gamma bank 2 vcom1 gamma bank 1 prog re f prog re f vcom1 vcom2 gamma bank 1 2:1 mux 2:1 mux dac gamma bank 2 mtp reg i 2 c reg control dac reg vcom amplifier 12 dacs 12 gamma buffers 12 part temp range pin-package MAX9679etg+ -40 n c to +85 n c 24 tqfn-ep* for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com.
2 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 functional diagram mtp memory prog re f i 2 c interface vcom 1 i 2 c reg prog re f vcom 1 vcom 2 dac reg prog re f gamma bank 1 gamma bank 1 gamma bank 1 vcom 1 vcom 2 gamma bank 2 gamma bank 2 sd a sc l dvdd a0 12 gam ma, 1 vcom MAX9679 bksel 10 10 dac agnd 10 dac 10 dac 10 dac 10 dac 10 dac 2:1 mux 2:1 mux 10 dac agnd 10 dac 10 dac 10 dac 10 dac 10 dac 10 dac prog re f v pref avdd1 avdd2 gma1 gma2 gma3 gma4 gma5 gma6 gma7 gma8 gma9 gma10 gma11 gma12 avdd_amp vcom vcom_fb agnd maxim integrated
3 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 typical application circuit mtp memory prog re f i 2 c interface tcon vcom 1 gamma bank 1 sd a sc l dvdd a0 12 gam ma, 1 vcom MAX9679 bksel 10 10 dac agnd 10 dac 10 dac 10 dac 10 dac 10 dac 2:1 mux 2:1 mux 10 dac agnd 10 dac 10 dac 10 dac 10 dac 10 dac 10 dac prog re f v pref avdd1 avdd2 hvdd hvdd to lcd panel gma1 gma2 gma3 gma4 gma5 gma6 gma7 gma8 gma9 gma10 gma11 gma12 avdd_amp vcom vcom_fb agnd i 2 c reg prog re f vcom 1 vcom 2 gamma bank 1 gamma bank 2 i 2 c reg prog re f vcom 1 vcom 2 gamma bank 1 gamma bank 2 serv ice driv er chip to lcd panel sou rce driv er chip pmic 12v maxim integrated
4 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 (all voltages are with respect to agnd.) supply voltages avdd1, avdd2, avdd_amp ............................ -0.3v to +22v dvdd ................................................................... -0.3v to +4v outputs gma1Cgma6 ................................... -0.3v to (v avdd1 + 0.3v) gma7Cgma12 ................................. -0.3v to (v avdd2 + 0.3v) vcom ....................................... -0.3v to (v avdd_amp + 0.3v) inputs sda, scl, a0, bksel ......................................... -0.3v to +6v vcom_fb ................................. -0.3v to (v avdd_amp + 0.3v) continuous current sda, scl ..................................................................... q 20ma gma1Cgma8 ............................................................. q 200ma vcom ........................................................................ q 600ma continuous power dissipation (t a = +70 n c) tqfn multilayer board (derate 25.6mw/ n c above +70 n c) ......................... 2051.3mw junction temperature ..................................................... +125 n c operating temperature range .......................... -40 n c to +85 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c electrical characteristics (v avdd1 = 18v, v avdd2 = v avdd_amp = 9v, v dvdd = 3.3v, v agnd = 0v, vcom = vcom_fb, programmable reference code = 905, no load, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. tqfn junction-to-ambient thermal resistance ( q ja ) .......... 39c/w junction-to-case thermal resistance ( q jc ) ................. 6c/w package thermal characteristics (note 1) parameter symbol conditions min typ max units supplies avdd1 analog supply voltage range v avdd1 guaranteed by psrr 9 20 v avdd2 analog supply voltage range v avdd2 guaranteed by psrr 6 20 v avdd_amp analog supply voltage range v avdd_amp guaranteed by psrr 9 20 v digital supply voltage v dvdd 2.7 3.6 v slowest dvdd ramp-up time dvdd ramp-up time from 1.5v to 2.3v to ensure correct mtp loading 20 25 ms avdd1 analog quiescent current i avdd1 7 11 ma avdd2 quiescent current i avdd2 6 9 ma avdd_amp quiescent current i avdd_amp 5 8 ma digital quiescent current i dvdd no scl or sda transitions 1.5 3 ma thermal shutdown +160 n c thermal-shutdown hysteresis 15 n c undervoltage-lockout threshold uvlo dvdd undervoltage-lockout threshold 2.1 2.3 2.6 v analog supply voltage range for programming mtp 15 20 v maxim integrated
5 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 electrical characteristics (continued) (v avdd1 = 18v, v avdd2 = v avdd_amp = 9v, v dvdd = 3.3v, v agnd = 0v, vcom = vcom_fb, programmable reference code = 905, no load, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units programmable reference (v pref ) full-scale voltage referred to output, t a = +25 n c 19.96 19.98 20.00 v resolution 10 bits integral nonlinearity error t a = +25 n c, 336 p reference code p 1007 0.5 1 lsb differential nonlinearity error t a = +25 n c, 336 p reference code p 1007 0.5 1 lsb dac resolution 10 bits integral nonlinearity error t a = +25 n c, 16 p code p 1008 for gamma, 256 p code p 1008 for vcom 0.5 1 lsb differential nonlinearity error t a = +25 n c, 16 p code p 1008 for gamma, 256 p code p 1008 for vcom 0.5 1 lsb gamma short-circuit current output connected to either supply rail 200 ma total output error t a = +25 n c, code = 768 for gma1Cgma6 and code = 256 for gma7C gma12 40 mv load regulation -5ma p i load p +5ma, code = 768 for gma1Cgma6 and code = 256 for gma7Cgma12 0.5 mv/ma low output voltage sinking 4ma, referred to lower supply rail 0.15 0.2 v high output voltage sourcing 4ma, referred to upper supply rail -0.2 -0.15 v power-supply rejection ratio gma1Cgma6, code = 768, v avdd1 = 9v to 20v; gma7Cgma12, code = 256, v avdd2 = 5v to 20v 60 90 db gma1Cgma6, code = 768, frequency = 120khz; gma7Cgma12, code = 256, frequency = 120khz 40 output resistance buffer is disabled 78 k i maximum capacitive load placed directly at output 150 pf noise rms noise (10mhz bandwidth) 375 f v vcom output (vcom) short-circuit current output connected to either vcom amplifier supplies 600 ma total output error t a = +25 n c, code = 256, v avdd_amp = 9v and 20v 40 mv load regulation -80ma p i load p +80ma, code = 256 0.5 mv/ma low output voltage sinking 10ma, referred to lower supply rail 0.15 0.2 v high output voltage sourcing 10ma, referred to upper supply rail -0.2 -0.15 v maxim integrated
6 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 digital i/o characteristics (v dvdd = 3.3v, v agnd = 0v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) (note 2) i 2 c timing characteristics (v dvdd = 3.3v, v agnd = 0v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) (note 2) electrical characteristics (continued) (v avdd1 = 18v, v avdd2 = v avdd_amp = 9v, v dvdd = 3.3v, v agnd = 0v, vcom = vcom_fb, programmable reference code = 905, no load, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) note 2: 100% production tested at t a = +25 n c. specifications over temperature limits are guaranteed by design. parameter symbol conditions min typ max units power-supply rejection ratio 9v p v avdd_amp p 20v, code = 256 60 90 db frequency = 120khz, code = 256 40 maximum capacitive load placed directly at output 50 pf slew rate swing 4v p-p at vcom, 10% to 90%, r l = 10k i , c l = 50pf 100 v/ f s bandwidth r l = 10k i , c l = 50pf 60 mhz noise rms noise (10mhz bandwidth) 375 f v parameter symbol conditions min typ max units input high voltage v ih 0.7 x dvdd v input low voltage v il 0.3 x dvdd v hysteresis of schmitt trigger inputs v hys 0.05 x dvdd v low-level output voltage v ol open drain, i sink = 3ma 0 0.4 v low-level output current i ol v ol = 0.4v 20 ma input leakage current i ih , i il v in = 0 or dvdd -10 +0.01 +10 f a input capacitance 5 pf power-down input current i in dvdd = 0, v in = 1.98v -10 +10 f a parameter symbol conditions min typ max units serial-clock frequency f scl 0 1000 khz hold time (repeated) start condition t hd,sta after this period, the first clock pulse is generated 0.26 f s scl pulse-width low t low 0.5 f s scl pulse-width high t high 0.26 f s setup time for a repeated start condition t su,sta 0.26 f s data hold time t hd,dat i 2 c-bus devices 0 ns data setup time t su,dat 50 ns sda and scl receiving rise time t r 120 ns sda and scl receiving fall time t f 120 ns sda transmitting fall time t f 120 ns maxim integrated
7 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 i 2 c timing characteristics (continued) (v dvdd = 3.3v, v agnd = 0v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) (note 2) typical operating characteristics (v avdd1 = 18v, v avdd2 = v avdd_amp = 9v, v dvdd = 3.3v, v agnd = 0v, vcom = vcom_fb, programmable reference code = 905, no load, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) parameter symbol conditions min typ max units setup time for stop condition t su,sto 0.26 f s bus free time between stop and start conditions t buf 0.5 f s bus capacitance c b 550 pf data valid time t vd;dat 0.45 f s data valid acknowledge time t vd;ack 0.45 f s pulse width of suppressed spike t sp 0 50 ns gamma load regulation MAX9679 toc01 current load (a) gamma voltage (v) 7.91 7.92 7.93 7.94 7.95 7.90 -0.020 -0.015 -0.010 -0.005 0 0.005 0.010 0.015 0.020 vcom load regulation MAX9679 toc02 current load (ma) vcom voltage (v) 80 60 20 40 -60 -40 -20 0 -80 8.92 8.94 8.96 8.98 9.00 9.02 9.04 9.06 9.08 9.10 8.90 -100 100 vcom code x 1ff dnl (lsb) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 gamma dnl MAX9679 toc03 code 200 400 600 800 0 1000 inl (lsb) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 vcom inl MAX9679 toc06 code 200 400 600 800 0 1000 inl (lsb) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 gamma inl MAX9679 toc04 code 200 400 600 800 0 1000 dnl (lsb) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 vcom dnl MAX9679 toc05 code 200 400 600 800 0 1000 maxim integrated
8 MAX9679 typical operating characteristics (continued) (v avdd1 = 18v, v avdd2 = v avdd_amp = 9v, v dvdd = 3.3v, v agnd = 0v, vcom = vcom_fb, programmable reference code = 905, no load, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) gamma output vs. temperature MAX9679 toc07 temperature (c) gamma output voltage (v) 60 35 -15 10 9.965 9.970 9.975 9.980 9.990 9.985 9.995 10.000 9.960 -40 85 gamma code x 1ff bank switching settling time for gamma MAX9679 toc10 gma1 5v/div bksel 5v/div 200ns/div bank switching settling time for vcom MAX9679 toc08 bksel 2v/div vcom 5v/div 400ns/div bank switching settling time for gamma MAX9679 toc11 gma1 5v/div bksel 5v/div 200ns/div bank switching settling time for vcom MAX9679 toc09 vcom 5v/div bksel 5v/div 200ns/div frequency (hz) psrr (db) 1m 100k 10k 10m power-supply rejection ratio (gma = 9v) MAX9679 toc12 -50 -40 -30 -20 -10 0 -60 v avdd1 = 18v q 100mv p-p frequency (hz) psrr (db) 1m 100k 10k 10m power-supply rejection ratio (vcom = 9v) MAX9679 toc13 -50 -40 -30 -20 -10 0 -60 v avdd_amp = 18v q 100mv p-p maxim integrated 12-channel, 10-bit programmable gamma and vcom reference voltages
9 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 typical operating characteristics (continued) (v avdd1 = 18v, v avdd2 = v avdd_amp = 9v, v dvdd = 3.3v, v agnd = 0v, vcom = vcom_fb, programmable reference code = 905, no load, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) frequency (hz) psrr (db) 1m 10m 100k 10k power-supply rejection ratio (v pref = 2.5v) MAX9679 toc14 -50 -40 -30 -20 -10 0 -60 v avdd1 = 18v q 100mv p-p gamma load transient MAX9679 toc15 gma1 5v/div i out 100ma /div 2s/div vcom load transient MAX9679 toc16 v vcom 1v/div i out 200ma /div 2s/div gamma program to output delay MAX9679 toc17 gma1 5v/div scl 2v/div sda 2v/div 20s /div vcom program to output delay MAX9679 toc18 v vcom 5v/div scl 2v/div sda 2v/div 20s /div programmable reference vs. avdd1 supply voltage MAX9679 toc19 v avdd1 (v) v pref (v) 17 16 10 11 12 14 13 15 4.9605 4.9610 4.9615 4.9620 4.9625 4.9630 4.9635 4.9640 4.9600 91 8 programmable reference vs. temperature MAX9679 toc20 temperature (c) v pref (v) 80 35 -10 4.9600 4.9605 4.9610 4.9615 4.9620 4.9625 4.9630 4.9595 -55 125 maxim integrated
10 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 pin configuration pin description tqfn MAX9679 19 20 21 22 12 34 56 18 17 16 15 14 13 23 24 12 11 10 9 8 7 gma11 avdd2 gma12 avdd_amp vcom_fb agnd dvdd sc l sd a bksel a0 gma10 gma9 gma7 gma6 gma5 vcom gma4 gma2 gma3 gma1 agnd avdd1 gma8 top view + ep pin name function 1, 7 agnd analog ground 2 dvdd digital power supply. bypass dvdd with a 0.1 f f capacitor to agnd. 3 scl i 2 c-compatible serial-clock input 4 sda i 2 c-compatible serial-data input/output 5 bksel bank select logic input. selects which bank of volatile registers are switched through to the dacs. 6 a0 i 2 c-compatible device address bit 0 (input) 8 avdd1 analog power supply 1. the buffers for gma1 through gma6 operate from avdd1. bypass avdd1 with a 0.1 f f capacitor to agnd. 9 gma1 gamma dac analog output 1 10 gma2 gamma dac analog output 2 11 gma3 gamma dac analog output 3 12 gma4 gamma dac analog output 4 13 gma5 gamma dac analog output 5 14 gma6 gamma dac analog output 6 15 gma7 gamma dac analog output 7 16 gma8 gamma dac analog output 8 17 gma9 gamma dac analog output 9 18 gma10 gamma dac analog output 10 19 gma11 gamma dac analog output 11 20 gma12 gamma dac analog output 12 21 avdd2 analog power supply 2. the buffers for gma7 through gma12 operate from avdd2. bypass avdd2 with a 0.1 f f capacitor to agnd. 22 avdd_amp power supply for vcom amplifier. bypass avdd_amp with a 0.1 f f capacitor to agnd. 23 vcom vcom output 24 vcom_fb feedback for vcom amplifier. vcom_fb is the negative input terminal of the vcom operational amplifier. ep exposed pad. ep is internally connected to agnd. ep must be connected to agnd. maxim integrated
11 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 detailed description the MAX9679 combines gamma, vcom, and the dac reference voltage into a single chip. all the output voltages are programmable. power sequencing is well behaved since a single chip generates all the various reference voltages needed for the lcd panel. previous generations of programmable gamma chips required an external reference voltage for the digital-to-analog converters (dacs). this ic integrates a programmable reference voltage (v pref ) for the dacs, eliminating the need for an external reference voltage. accuracy of the full-scale programmable reference voltage is 0.1%, and resolution is 10 bits. both the dc and ac power-supply rejection of the programmable reference voltage is extremely high since it is powered from an internal linear regulator. the gamma outputs are divided into an upper bank (gma1Cgma6) that is powered from avdd1 and a lower bank (gma7Cgma12) that is powered from avdd2. avdd1 is the analog supply voltage for the lcd panel. avdd2 can be connected to the same supply as avdd1. if the ic's heat generation needs to be reduced, avdd2 can be connected to a lower voltage such as 12v (input voltage to the lcd panel) or hvdd (half of the avdd1 supply). the vcom operational amplifier operates from avdd_amp. similar to avdd2, avdd_amp can be connected to avdd1, 12v, or hvdd. peak vcom out - put current is 600ma. the negative input terminal of the vcom operational amplifier is available for applica - tions that require external push-pull transistors. the ic contains nonvolatile, multiple-time programmable memory that can store the gamma, vcom, and the pro - grammable reference codes. the interface and control of the ic are completely digi - tal. functions that are not real-time such as gamma and vcom are set through the i 2 c interface. real-time func - tions, such as the switching of the gamma and vcom, are done through the dedicated logic input signal bksel. programmable reference the ic has an internal programmable reference, which when referred to the output, has a full-scale voltage of 20v ( q 0.1%). the reference voltage is calculated using the following equation: v pref = (20v code)/2 n where code is the numeric value stored in register address and n is the bits of resolution. for the ic, n = 10 and code ranges from 0 to 1023. note that v pref cannot be 20v because the maximum value of code is always one lsb less than the full-scale voltage. when the programmable reference code is 1023, then v pref is: v pref = (20v 1023)/2 10 = 19.98v 10-bit digital-to-analog converters v pref sets the full-scale output of the dacs. determine the output voltages using the following equations: v gma_ = (v pref code)/2 n v vcom = (v pref code)/2 n where code is the numeric value of the dacs binary input code and n is the bits of resolution. for the ic, n = 10 and code ranges from 0 to 1023. note that the dac can never output v pref because the maximum value of code is always one lsb less than the reference. for example, if v pref = 16v and the dac code is 1023, then the gamma output voltage is: v gma_ = (16v 1023)/2 10 = 15.98438v gamma buffers the gamma buffers can typically source or sink 4ma of dc current within 200mv of the supplies. the source drivers can kick back a great deal of current to the buffer outputs during a horizontal line change or a polarity switch. the dac output buffers can source/sink 200ma of peak transient current to reduce the recovery time of the output voltages when critical levels and pat - terns are displayed. vcom amplifier the operational amplifier attached to the vcom dac holds the vcom voltage stable while providing the ability to source and sink 600ma into the backplane of a tft- lcd panel. the operational amplifier can directly drive the capacitive load of the tft-lcd backplane without the need for a series resistor in most cases. the vcom amplifier has current limiting on its output to protect its bond wires. if the application requires more than 600ma, buffer the output of the vcom amplifier with a max9650, a vcom power amplifier. the max9650 can source or sink 1.3a of current. maxim integrated
12 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 switching gamma and vcom the ic can keep two independent sets of gamma and vcom codes in volatile memory (table 1). the bksel signal determines which set of gamma and vcom codes is driven out ( table 2 ). multiple-time programmable (mtp) memory mtp memory, which is a form of nonvolatile memory, stores the dac code values even when the chip is not powered. when the chip is powered up, the code values are automatically transferred from mtp memory to the i 2 c registers. see the power-on reset (por)/power-up section for more details. the user can program dac codes into mtp memory up to 100 times. power-on reset (por)/power-up the por circuit that monitors dvdd ensures that all i 2 c registers are reset to their mtp values upon power-up or por. once dvdd rises above 2.4v (typ), the por circuit releases the i 2 c registers and the values stored in mtp are loaded. should dvdd drop to less than 2.4v typical, then the contents of the registers can no longer be guaranteed and a reset is generated. when dvdd rises back above the por voltage, the values stored in mtp are loaded back into the i 2 c registers. the transfer time of the mtp registers to i 2 c registers is 300 f s typi - cal and is less than 400 f s in the worst case. during this time, avdd should not be powered up, and the i 2 c does not acknowledge any commands. the i 2 c only starts acknowledging commands after all registers have been loaded from mtp. thermal shutdown the ic features thermal-shutdown protection with tem - perature hysteresis. when the die temperature reaches +165 n c, all of the gamma outputs and the vcom output are disabled. when the die cools down by 15 n c, the outputs are enabled again. register and bit descriptions the ic has both volatile memory and also nonvolatile mtp memory. the volatile memory structure has i 2 c reg - isters and dac registers (see the functional diagram ). the i 2 c master must first write data into the i 2 c registers of the ic before the data can be moved into the dac registers (or mtp memory). the advantage of having the i 2 c registers serve as a data buffer for the ic is that data can be transferred in a parallel operation from the i 2 c registers to the dac registers, and so the entire gamma curve is essentially updated instantaneously rather than serially on a point-by-point basis. the volatile memory stores two independent sets of gamma curves and vcom codes. the first set consists of gamma codes from bank 1, vcom1 code, vcom1min code, and vcom1max code. the second set consists of gamma codes from bank 2, vcom2 code, vcom2min code, and vcom2max code. in addition, volatile memo - ry stores the programmable reference code. table 1. registers in each of the two independent sets table 2. bksel logic table registers in set 1 registers in set 2 gma1bk1 gma1bk2 gma2bk1 gma2bk2 gma3bk1 gma3bk2 gma4bk1 gma4bk2 gma5bk1 gma5bk2 gma6bk1 gma6bk2 gma7bk1 gma7bk2 gma8bk1 gma8bk2 gma9bk1 gma9bk2 gma10bk1 gma10bk2 gma11bk1 gma11bk2 gma12bk1 gma12bk2 vcom1 vcom2 vcom1min vcom2min vcom1max vcom2max output bksel = low bksel = high gma1 gma1bk1 gma1bk2 gma2 gma2bk1 gma2bk2 gma3 gma3bk1 gma3bk2 gma4 gma4bk1 gma4bk2 gma5 gma5bk1 gma5bk2 gma6 gma6bk1 gma6bk2 gma7 gma7bk1 gma7bk2 gma8 gma8bk1 gma8bk2 gma9 gma9bk1 gma9bk2 gma10 gma10bk1 gma10bk2 gma11 gma11bk1 gma11bk2 gma12 gma12bk1 gma12bk2 vcom vcom1 vcom2 maxim integrated
13 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 the nonvolatile mtp memory stores all the data except for the second set of gamma curves and vcom codes. during power-up, the codes in the mtp memory are transferred into the i 2 c and dac registers. each memory location whether in nonvolatile or volatile memory holds a 10-bit word. two bytes must be read or written through the i 2 c interface for every register. table 3 shows the register map. the same register address and register name exists in the mtp memory bank, i 2 c register bank, and the dac register bank. the write control bits determine into which memory location the data is stored. register description only the 10 least significant bits (lsbs) are written to the registers ( table 4 ). during a write operation, the write control bits (the two msbs) are stripped from the incom - ing data stream and are used to determine whether the mtp or dac registers are updated ( table 5 ). note the i 2 c registers are only 10 bits. table 3. register map register address register name register description power-on reset value mtp factory initialization value 0x00 gma1bk1 gamma 1 of bank 1 0x200 0x200 0x01 gma2bk1 gamma 2 of bank 1 0x200 0x200 0x02 gma3bk1 gamma 3 of bank 1 0x200 0x200 0x03 gma4bk1 gamma 4 of bank 1 0x200 0x200 0x04 gma5bk1 gamma 5 of bank 1 0x200 0x200 0x05 gma6bk1 gamma 6 of bank 1 0x200 0x200 0x06 gma7bk1 gamma 7 of bank 1 0x200 0x200 0x07 gma8bk1 gamma 8 of bank 1 0x200 0x200 0x08 gma9bk1 gamma 9 of bank 1 0x200 0x200 0x09 gma10bk1 gamma 10 of bank 1 0x200 0x200 0x0a gma11bk1 gamma 11 of bank 1 0x200 0x200 0x0b gma12bk1 gamma 12 of bank 1 0x200 0x200 0x0c reserved 0x000 0x0d reserved 0x000 0x0e reserved 0x000 0x0f reserved 0x000 0x10 reserved 0x000 0x11 reserved 0x000 0x12 vcom1 common voltage 1 0x200 0x200 0x13 reserved 0x000 0x14 reserved 0x000 0x15 reserved 0x000 0x16 reserved 0x000 0x17 reserved 0x000 0x18 vcom1min minimum vcom1 value 0x000 0x000 0x19 vcom1max maximum vcom1 value 0x3ff 0x3ff 0x1a reserved 0x000 0x1b reserved 0x000 0x1c reserved 0x000 0x1d reserved 0x000 0x1e reserved 0x000 maxim integrated
14 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 table 3. register map (continued) table 4. register description register address register name register description power-on reset value mtp factory initialization value 0x1f vpref programmable reference voltage 0x200 0x200 0x20 gma1bk2 gamma 1 of bank 2 0x200 0x21 gma2bk2 gamma 2 of bank 2 0x200 0x22 gma3bk2 gamma 3 of bank 2 0x200 0x23 gma4bk2 gamma 4 of bank 2 0x200 0x24 gma5bk2 gamma 5 of bank 2 0x200 0x25 gma6bk2 gamma 6 of bank 2 0x200 0x26 gma7bk2 gamma 7 of bank 2 0x200 0x27 gma8bk2 gamma 8 of bank 2 0x200 0x28 gma9bk2 gamma 9 of bank 2 0x200 0x29 gma10bk2 gamma 10 of bank 2 0x200 0x2a gma11bk2 gamma 11 of bank 2 0x200 0x2b gma12bk2 gamma 12 of bank 2 0x200 0x2c vcom2 common voltage 2 0x200 0x2d vcom2min minimum vcom2 value 0x000 0x2e vcom2max maximum vcom2 value 0x3ff reg reg addr b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma1bk1 0x00 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma2bk1 0x01 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma3bk1 0x02 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma4bk1 0x03 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma5bk1 0x04 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma6bk1 0x05 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma7bk1 0x06 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma8bk1 0x07 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma9bk1 0x08 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma10bk1 0x09 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma11bk1 0x0a w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma12bk1 0x0b w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 reserved 0x0c reserved 0x0d reserved 0x0e reserved 0x0f reserved 0x10 reserved 0x11 vcom1 0x12 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 maxim integrated
15 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 table 4. register description (continued) table 5. write control bits reg reg addr b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 reserved 0x13 reserved 0x14 reserved 0x15 reserved 0x16 reserved 0x17 vcom1min 0x18 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 vcom1max 0x19 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 reserved 0x1a reserved 0x1b reserved 0x1c reserved 0x1d reserved 0x1e vpref 0x1f w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma1bk2 0x20 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma2bk2 0x21 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma3bk2 0x22 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma4bk2 0x23 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma5bk2 0x24 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma6bk2 0x25 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma7bk2 0x26 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma8bk2 0x27 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma9bk2 0x28 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma10bk2 0x29 w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma11bk2 0x2a w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 gma12bk2 0x2b w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 vcom2 0x2c w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 vcom2min 0x2d w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 vcom2max 0x2e w1 w0 x x x x b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 w1 w0 action 0 0 no update. 0 1 mtp registers get updated when the current i 2 c register has finished updating. see the nonvolatile memory section for more details. 1 0 all dac registers get updated when the current i 2 c register has finished updating (end of b0). 1 1 no update. maxim integrated
16 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 vcom programmable range (vcommin and vcommax) the ic features a programmable range for vcom1 and vcom2. vcom1min and vcom1max registers provide low and high limits for the vcom1 register. at the factory, vcom1min is set to 0 and vcom1max is set to 1023 (default values) to provide the full rail-to-rail programmable range for vcom1. later, the user can define their own limits by programming vcom1min and vcom1max registers and mtp. vcom1 register values are limited to the defined range. if the vcom1 register accidentally gets programmed with a value higher than vcom1max, it automatically gets locked to the vcom1max value. the i 2 c bus does acknowledge and receive the data sent on the bus; however, internally the part recognizes that the value is outside of the range and adjusts it accordingly. the same scenario is true if the value programming vcom1 is below vcom1min. vcom2min and vcom2max have a similar relationship with vcom2. memory the ic includes both volatile memory (i 2 c registers and dac registers) and nonvolatile memory (mtp registers). it is possible to write to each single volatile memory reg - ister from a mtp register individually or to write to all at once through memory write bits (m1, m0), which are the two msbs of the register address byte. table 6 shows the memory write bits. set both m1 and m0 to low or high when writing to or reading from the i 2 c registers through the i 2 c bus. volatile memory the ic features a double-buffered register structure with the i 2 c registers as the first buffer and the dac registers as the second buffer. the benefit is that the i 2 c registers can be updated without updating the dac registers. after the i 2 c registers have been updated, the value or values in the i 2 c registers can be transferred all at the same time to the dac registers. figure 1 shows how to program a single dac register. the output voltage is updated after sending lsb (d0). it is possible to write to multiple i 2 c registers first, then update the output voltage of all channels simultane - ously, as shown in figure 2. in this mode, it is pos - sible for the i 2 c master to write to all registers of the ic (gamma, vcom, and programmable reference) in one communication. in that case, the value programmed on addresses 0x0cC0x11, 0x13C0x17, 0x1aC0x1e, and 0x20C0x2e are meaningless. however, the ic does send an acknowledge bit for each of the two bytes on any of these addresses. the control bits (w1, w0) shown in figure 2 are set in a way that all dacs are programmed to their desired value with no changes to the output volt - ages until the lsb of the last dac is received and then all the channels update simultaneously. table 6. memory write bits figure 1. single dac programming m1 m0 action 0 0 none. 0 1 only the addressed i 2 c registers and dac registers get set to the mtp values. 1 0 all i 2 c registers and dac registers get set to the mtp values. 1 1 none. slave id dac/vcom address m1 s r/w = 0 a 11101 0b 10 0d 5d 4d 3d 2d 1d 0a m0 a 10 xxxx d9 d7 d6 d5 d4 d3 d2 d1 d0 ap d8 data data maxim integrated
17 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 nonvolatile memory the ic is able to write to nonvolatile memory (mtp) of any single dac/vcom register in a single or burst i 2 c trans - action. this memory can be written to at least 100 times. figure 3 shows a single write to a mtp address. the control bits are set in a way that the mtp register is updated at the end of lsb (d0). figure 4 shows how to program multiple mtp registers in one communication transition. similar to programming the volatile memory, the first 2 bytes of data correspond to the dac/vcom address specified by the master on the previous byte and the following 2 bytes of data correspond to the next address and so on. in this con - figuration, all the mtp registers are programmed at the same time following the lsb of the last set of data byte. the last set of data bytes is different than the previous bytes because bit 15 and bit 14 are 0b0 and 0b1, respectively. if, for some reason, the master issues a stop condition before sending the last two bytes of the data with appropriate values of bit 15 (0b0) and bit 14 (0b1), then none of the mtp registers are updated. programming the mtp registers also updates the dac registers and consequently the output voltages. similar to multiple volatile memory programming, the update only occurs after the lsb of the last byte is received. all the outputs are programmed and updated simultane - ously; however, depending on the number of mtp regis - ters: it takes 31ms to 500ms to store the values into the nonvolatile memory. during this time, the ic is not avail - able on the i 2 c bus and any communication from the master should be delayed until the mtp is programmed. any attempt from the i 2 c master to talk to the ic is not acknowledged. general and single acquire commands it is possible to update all the dac outputs to the previ - ously stored mtp values with one special command. set the 2 msb bits (m1 and m0) of the register address to 0b10 to set all the i 2 c registers, dac registers and the output voltages to the values of mtp ( figure 5). the ic ignores the rest of the register address in this case. it is also possible to update the i 2 c register, dac regis - ter and dac output voltage of only one channel from the mtp. set the 2 msb bits (m1 and m0) of the dac/vcom address to 0b01 ( figure 6) to move a specific value from mtp into the i 2 c register and dac register of a single channel. . figure 2. multiple (or all) dacs programming slave id dac/vcom address m1 s r/w = 0 a 111010 b1 00 d5 d4 d3 d2 d1 d0 a m0 a 00 x xxx d9 d7 d6 d5 d4 d3 d2 d1 d0 a d8 data data a 00 x xxx d9 d7 d6 d5 d4 d3 d2 d1 d0 a d8 data data a 10 x xxx d9 d7 d6 d5 d4 d3 d2 d1 d0 ap d8 data data maxim integrated
18 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 figure 3. single mtp programming figure 4. multiple mtp programming figure 5. general acquire command to updated all outputs with mtp figure 6. single acquire command to updated one output with mtp slave id dac/vcom address m1 s r/w = 0 a 1 11010 b1 00 d5 d4 d3 d2 d1 d0 a m0 a 01 x xxx d9 d7 d6 d5 d4 d3 d2 d1 d0 ap d8 data data slave id dac/vcom address m1 s r/w = 0 a 111010 b1 00 d5 d4 d3 d2 d1 d0 a m0 a 00 x xxx d9 d7 d6 d5 d4 d3 d2 d1 d0 a d8 data data a 00 x xxx d9 d7 d6 d5 d4 d3 d2 d1 d0 a d8 data data a 01 x xxx d9 d7 d6 d5 d4 d3 d2 d1 d0 ap d8 data data slave id m1 s r/w = 0 a 111010 b1 10000000 a m0 p dac/vcom address m1 s r/w = 0 a 111010 b1 01 d5 d4 d3 d2 d1 d0 a m0 p slave id maxim integrated
19 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 smbus is a trademark of intel corp. i 2 c serial interface the ic features an i 2 c/smbus k -compatible, 2-wire serial interface consisting of a serial-data line (sda) and a serial-clock line (scl). sda and scl facilitate com - munication between the devices and the master at clock rates up to 1mhz. figure 7 shows the 2-wire interface timing diagram. the master generates scl and initiates data transfer on the bus. a master device writes data to the devices by transmitting the proper slave address followed by the register address and then the data word. each transmit sequence is framed by a start (s) or repeated start (sr) condition and a stop (p) con - dition. each word transmitted to the MAX9679 is 8 bits long and is followed by an acknowledge clock pulse. a master reading data from the devices transmits the proper slave address followed by a series of nine scl pulses. the devices transmit data on sda in sync with the master-generated scl pulses. the master acknowl - edges receipt of each byte of data. each read sequence is framed by a start (s) or repeated start (sr) condition, a not acknowledge, and a stop (p) condi - tion. sda operates as both an input and an open-drain output. a pullup resistor, typically greater than 500 i , is required on the sda bus. scl operates as only an input. a pullup resistor, typically greater than 500 i , is required on scl if there are multiple masters on the bus, or if the master in a single-master system has an open-drain scl output. series resistors in line with sda and scl are optional. series resistors protect the digital inputs of the devices from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. bit transfer one data bit is transferred during each scl cycle. the data on sda must remain stable during the high period of the scl pulse. changes in sda while scl is high are control signals. see the start and stop conditions section. sda and scl idle high when the i 2 c bus is not busy. start and stop conditions sda and scl idle high when the bus is not in use. a master initiates communication by issuing a start (s) condition. a start condition is a high-to-low transition on sda with scl high. a stop (p) condition is a low-to- high transition on sda while scl is high ( figure 8 ). a start condition from the master signals the beginning of a transmission to the ic. the master terminates trans - mission, and frees the bus, by issuing a stop condition. the bus remains active if a repeated start (sr) con - dition is generated instead of a stop condition. figure 8. start, stop, and repeated start conditions scl sda ss rp figure 7. i 2 c interface timing diagram scl sda start condition stop condition repeated start condition start condition t hd,sta t su,sta t hd,sta t sp t buf t su,sto t low t su,dat t hd,dat t high t r t f maxim integrated
20 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 early stop conditions the ic recognizes a stop condition at any point during data transmission except if the stop condition occurs in the same high pulse as a start condition. for proper operation, do not send a stop condition during the same scl high pulse as the start condition. slave address the slave address is defined as the 7 most significant bits (msbs) followed by the read/write (r/w) bit. set the r/w bit to 1 to configure the ic to read mode. set the r/w bit to 0 to configure the ic to write mode. the address is the first byte of information sent to the ic after the start condition. the ics slave address is configured with a0. table 7 shows the possible addresses for the ic. acknowledge the acknowledge bit (ack) is a clocked 9th bit that the ic uses to handshake receipt of each byte of data when in write mode ( figure 9 ). the ic pulls down sda during the entire master-generat - ed ninth clock pulse if the previous byte is successfully received. monitoring ack allows for detection of unsuc - cessful data transfers. an unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data trans - fer, the bus master may retry communication. the master pulls down sda during the ninth clock cycle to acknowl - edge receipt of data when the ic is in read mode. an acknowledge is sent by the master after each read byte to allow data transfer to continue. a not acknowledge is sent when the master reads the final byte of data from the ic, followed by a stop condition. write data format a write to the ic consists of transmitting a start condi - tion, the slave address with the r/w bit set to 0, one data byte of data to configure the internal register address pointer, one word (2 bytes) of data or more, and a stop condition. figure 10 illustrates the proper frame format for writing one word of data to the ic. figure 11 illustrates the frame format for writing n-bytes of data to the ic. the slave address with the r/w bit set to 0 indicates that the master intends to write data to the ic. the ic acknowledges receipt of the address byte during the master-generated 9th scl pulse. the second byte transmitted from the master configures the ics internal register address pointer. the ics inter - nal address pointer consists of the six least significant bits (lsb) of the second byte. the 2 msbs of the second byte (m1 and m0) are set to 00b when writing to the inter - nal registers. see the memory section for more details. the pointer tells the ic where to write the next byte of data. an acknowledge pulse is sent by the ic upon receipt of the address pointer data when writing to the figure 9. acknowledge figure 10. writing a word of data to the ic table 7. slave address 1 scl start condition sda 28 9 clock pulse for acknowledgment acknowledge not acknowledge one word acknowledge from the ic a ap 0 acknowledge from the ic r/w s slave address register address data byte 2 autoincrement internal register address pointer a0 0 data byte 1 acknowledge from the ic acknowledge from the ic w1 w0 d9 d8 x xx xd 7d 6 d1 d0 d2 d4 d3 d5 m0 m1 a/a a0 read address write address agnd e9h (11101001) e8h (11101000) dvdd ebh (11101011) eah (11101010) maxim integrated
21 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 dac registers. when writing to the mtp, a not acknowl - edge is sent from the ic after the master writes the final byte of data, followed by a stop condition. the third and fourth bytes sent to the ic contain the data that is written to the chosen register and which type of register it writes to, volatile (dac) or nonvolatile memory (mtp). see the nonvolatile memory section for more details. an acknowledge pulse from the ic signals receipt of each data byte. the address pointer autoincre - ments to the next register address after receiving every other data byte. this autoincrement feature allows a master to write to sequential register address locations within one continuous frame. the master signals the end of transmission by issuing a stop condition. if data is written into register address 0x2e, the address pointer autoincrements to 0xff and stays at 0xff until the mas - ter writes a new value into the register address pointer. read data format the master presets the address pointer by first sending the ics slave address with the r/w bit set to 0 followed by the register address with m1 and m0 set to 00 after a start condition. the ic acknowledges receipt of its slave address and the register address by pulling sda low during the 9th scl clock pulse. a repeated start condition is then sent followed by the slave address with the r/w bit set to 1. the ic transmits the contents of the specified register. transmitted data is valid on the rising edge of the master-generated serial clock (scl). the address pointer autoincrements after every other read figure 12. reading one indexed word of data from the ic figure 11. writing n-bytes of data to the ic a 0s r acknowledge from the ic r/w s autoincrement interna l register address pointer a0 0 acknowledge from the ic one word not acknowledge from master aa p acknowledge from master xx d9 d8 x xx xd 7d 6d 1d 0 d2 d4 d3 d5 m0 m1 1a repeated start r/w slave address register address slave address data byte 1 data byte 2 acknowledge from the ic one word acknowledge the ic a aa 0 acknowledge from the ic r/w s slave address register address data byte 2 autoincrement internal register address pointer a0 0 data byte 1 acknowledge from the ic acknowledge from the ic w1 w0 d9 d8 x xx xd 7d 6d 1d 0 d2 d4 d3 d5 one word acknowledge from the ic a a/a p data byte n data byte n-1 acknowledge from the ic w1 w0 d9 d8 x xx xd 7d 6d 1d 0 d2 d4 d3 d5 m0 m1 maxim integrated
22 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 figure 13. reading n bytes of indexed data from the ic data byte. this autoincrement feature allows all registers to be read sequentially within one continuous frame. a stop condition can be issued after any number of read data bytes. if a stop condition is issued followed by another read operation, the first data byte to be read is from the register address location set by the previous transaction and not 0x00, and subsequent reads autoin - crement the address pointer until the next stop condi - tion. attempting to read from register addresses higher than 0x2e results in repeated reads from a dummy register containing all one data. the master acknowl - edges receipt of each read byte during the acknowledge clock pulse. the master must acknowledge all correctly received bytes except the last byte. the final byte must be followed by a not acknowledge from the master and then a stop condition. figure 12 and figure 13 illustrate the frame format for reading data from the ic. applications information power sequencing avdd1, avdd2, avdd_amp, and dvdd are indepen - dent of each other and can be powered up and powered down in any sequence. however, output voltages are only guaranteed to power up in a well-behaved manner when dvdd is powered up first and powered down last with 1ms allowed between dvdd and avdd ( figure 14 and figure 15). connecting avdd2 and avdd_amp to half avdd supply reduces the temperature of the ic. if avdd2 and avdd_amp are connected to the 12v supply to the lcd module because a half avdd supply is not available, then figure 16 shows the power-up and power-down sequence. the gamma and vcom outputs are close to ground until avdd1 is greater than its pow - er-on reset voltage because avdd1 is used to power the internal voltage reference. dvdd must be powered up within 25ms from 1.5v to 2.3v to ensure proper mtp loading/read. see figure 17. pcb layout and grounding if the ic is mounted using reflow soldering or waver soldering, the ground vias for the exposed pad should have a finished hole size of at least 14 mils to ensure adequate wicking of soldering onto the exposed pad. if the ic is mounted using solder mask technique, the vias requirement does not apply. in either case, the exposed pad on the tqfn package is electrically connected to both digital and analog grounds through a low thermal resistance path to ensure adequate heat dissipation. do not route traces under these packages. the layout of the exposed pad should have multiple small vias over a single large via as shown in figure 1 8 . thermal resistance between top and ground layers can be optimized with multiple small vias, and it is recommended to have a plated via with 15 mils diameter. the via should be flooded with solder for good thermal performance. power-supply bypassing the ic operates from a single 9v to 20v analog sup - ply (avdd) and a 2.7v to 3.6v digital supply (dvdd). bypass avdd to agnd with 0.1 f f and 10 f f capacitors in parallel. use an extensive ground plane to ensure optimum performance. bypass dvdd to agnd with a 0.1 f f capacitor. the 0.1 f f bypass capacitors should be as close as possible to the device. refer to the MAX9679 evaluation kit for a proven pcb layout. a 0s r sa 00 one word not acknowledge from master aa p acknowledge from master xx d9 d8 x xx xd 7d 6d 1d 0 d2 d4 d3 d5 m0 m1 1a autoincrement interna l register address pointer one word acknowledge from master aa acknowledge from master xx d9 d8 x xx xd 7d 6d 1d 0 d2 d4 d3 d5 repeated start slave address register address slave address data byte 1 data byte 2 data byte n data byte n-1 r/w r/w acknowledge from the ic acknowledge from the ic acknowledge from the ic maxim integrated
23 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 figure 14. conventional power-up and power-down sequence figure 15. power-up and power-down sequence with avdd2 and avdd_amp connected to half avdd figure 16. power-up and power-down sequence with avdd2 and avdd_amp connected to 12v dvdd >1ms dvdd time voltag e avdd1 = avdd2 = avdd_amp avdd1 = avdd2 = avdd_amp time voltag e avdd 1 avdd 1 dvdd avdd2 = avdd_amp avdd2 = avdd_amp dvdd >1ms dvdd dvdd avdd1 avdd1 avdd2 = avdd_amp avdd2 = avdd_amp time voltag e >1ms maxim integrated
24 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 figure 18. multiple small vias are recommended over a single large via in the pcb layout figure 17. dvdd power up requirement not recommended recommended uvlo < dvdd < mtp_por : no effect dvdd < uvlo : ic reset 1.5v 2.3v dvdd 3.3v 2.3v 1.5v dvdd 3.3v t start < 25ms : normal startup mtp_por 2.3v uvlo 1.5v mtp_por 2.3v case 1 normal startup case 2 very slow startup uvlo 1.5v t start > 25ms : mtp not read gamma, vcom = default (5v) maxim integrated
25 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 package type package code package code land pattern no. 24 tqfn t2444m+1 21-0139 90-0068 package information for the latest package outline information and land patterns (footrprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. maxim integrated
26 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 package information (continued) for the latest package outline information and land patterns (footrprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. maxim integrated
27 12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 package information (continued) for the latest package outline information and land patterns (footrprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. maxim integrated
12-channel, 10-bit programmable gamma and vcom reference voltages MAX9679 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. 28 maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 ? 2013 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 7/11 initial release 1 1/13 added ramp-up time parameter to electrical characteristics table, added new figure 17 and updated power sequencing section and figures 14C16 4, 22C24 2 5/13 added minimum value and removed the maximum value to the slowest dvdd ramp- up time parameter 4

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